The present invention relates to a semiconductor device and a method of forming the same, and particularly to a semiconductor device formed with elements having floating gates and a method of forming the same.
In a semiconductor device with a plurality of elements formed on a semiconductor substrate, there are formed element isolation films and channel stop diffusion layers for electrically separating the elements from each other.
For example, as shown in FIG. 5, a semiconductor device formed with elements having floating gates includes a semiconductor substrate 30, each element isolation film 31, each channel stop diffusion layer 32 and elements 33. The element isolation film 31, being made of an oxide film, is formed on the semiconductor substrate 30. The channel stop diffusion layer 32 is formed along the lower surface of the element isolation film 31 by diffusion of conductive impurities in the semiconductor substrate 30. The elements 33 are formed on regions separated from each other by means of each element isolation film 31 and each channel diffusion layer 32. The element 33 is thus constituted of a portion of the semiconductor substrate 30 in spaced-apart relation from each other by the element isolation film 30, a gate insulating film 301 formed on the semiconductor substrate 30, and a conductive layer 302 formed on the gate insulating layer 301. The conductive layer 302 includes a floating gate 303 and a control gate 305. The floating gate 303 is disposed on the upper surface of the gate insulating film 301 such that both the ends thereof are overlapped on the edge portions of the adjacent element isolation films 31. The surface of the floating gate 303 is covered with an insulating film 304. The control gate 305 is disposed on the insulating film 304 and on the element isolation film 31.
In the semiconductor device 3 formed with the elements 33 having the floating gates 303, electric charge is injected or discharged to or from each floating gate 303 for writing or erasing information to or from each element 33. In this case, each control gate 305 is possibly applied with a high voltage of about 20 V. The element isolation film 31 and the channel stop diffusion layer 32 thus require an element separating ability for preventing the formation of a parasitic MOS between the element 33a (33) and 33b (33) even when the voltage of 20 V is applied to the control gate 305. The element isolation ability is dependent on the film thickness of the element isolation film 31 and the impurity concentration in the channel stop diffusion layer 32.
For this reason, in the semiconductor device 3, the film thickness of the element isolation film 31 and the impurity concentration in the channel stop diffusion layer 32 are determined such that the conducting type of a portion of the semiconductor substrate 30 positioned under the element isolation film 31 is not inverted even when the above-described high voltage is applied to the control gate 305.
Another example of the semiconductor device formed with elements having floating gates is shown in FIG. 6. In this semiconductor device 4, the channel stop diffusion layer in the semiconductor device shown in FIG. 5 is of a two-layer structure of a first channel stop diffusion layer 42 and a second channel stop diffusion layer 43. The first channel stop diffusion layer 42 is formed along the lower surface of an element isolation film 41 formed on a semiconductor substrate 40. The second channel stop diffusion layer 43 is formed under the element isolation film 41 at a position where a control gate 403 is directly disposed on the upper surface of the element isolation film 41. The second channel stop diffusion layer 43 is denser in the diffused impurity concentration than the first channel stop diffusion layer 42.
In the semiconductor device 4, the film thickness of the element isolation film 41 and the diffused ion concentrations of the first and second channel stop diffusion layers 42 and 43 are determined such that at least the conducting type of a portion of the semiconductor substrate 40 corresponding to the second channel stop diffusion layer 43 is not inverted.
The element isolation film, however, tends to be thinned with the recent advance in the fining of the semiconductor device. Accordingly, to positively separate the elements 33a (33) and 33b (33) from each other in the semiconductor device 3 shown in FIG. 5, it is required to increase the diffused impurity concentration of the channel stop diffusion layer 32. However, the increase in the concentration of the channel diffusion layer 32 causes an inconvenience in that the withstand voltage of a diffusion layer (not shown) formed on the semiconductor substrate 30 for forming the element 33 is reduced at the edge portions of the element isolation film 31. Thus, the increase in the diffused impurity concentration of the channel stop diffusion layer 32 has a limitation, and therefore, to keep the element isolation ability to some extent, the film thickness of the element isolation film 31 must be kept to be thick somewhat. This obstructs the fining of the semiconductor device.
In the semiconductor device 4 having the construction shown in FIG. 6, the second channel stop diffusion layer positively separates the elements 44a (44) and 44b (44) from each other, and the reduction in the withstand voltage of a diffusion layer (not shown) for forming the element 44 is prevented by suppressing the diffused ion concentration of the first channel stop diffusion layer 42 positioned at the edge portions of the element isolation film 41. Accordingly, as compared with the film thickness of the element isolation film of the semiconductor device having the single channel stop diffusion layer, the film thickness of the element isolation film 41 can be reduced.
However, in the formation of the semiconductor device 4, there are required two steps of ion implantation for forming the first and second channel stop diffusion layers 42 and 43, thereby complicating the forming process compared with the formation of the semiconductor device 3 shown in FIG. 3.